This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-265773, filed Sep. 11, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, particularly relates to a semiconductor memory having a hierarchical bit line structure, for example, a semiconductor memory for use in a NOR type flash memory.
2. Description of the Related Art
There is a NOR type flash memory as one of the nonvolatile semiconductor memories.
FIG. 9 is an equivalent circuit diagram showing a part of a memory cell array in the NOR type flash memory.
Memory cell transistors (hereinafter referred to as xe2x80x9ccell transistorxe2x80x9d) are arrayed in a matrix form on a semiconductor substrate, control gates of the cell transistors are connected to corresponding word lines WL0 to WLn. Bit lines BL0 to BLm are provided on a CVD oxide film of the semiconductor substrate where the cell transistors are formed. Drains of the cell transistor are connected to corresponding bit lines BL0 to BLm.
FIG. 10 shows a sectional view of the cell transistor in FIG. 9. The cell transistor has a MOSFET structure in which a floating gate is formed on the semiconductor substrate through a tunnel oxide film and the control gate is formed on the floating gate through an inter-gate insulating film. A threshold voltage of the cell transistor is varied by the number of electrons stored in the floating gate.
FIG. 11 shows a relationship between a control gate voltage and a drain current of the cell transistor shown in FIG. 10.
A state in which the relatively many electrons are stored in the floating gate and the threshold voltage Vt of the cell transistor is high is defined as xe2x80x9c0xe2x80x9d data. On the contrary, a state in which the relatively few electrons are stored in the floating gate and the threshold voltage Vt is low is defined as xe2x80x9c1xe2x80x9d data.
Voltage applied to the control gate of the cell transistor (word line voltage) is varied by operating modes. Table 1 shows an example of bias conditions of data read, data write, and data erase for the cell transistor. Where Vg is a control gate voltage, Vd is a drain voltage, and Vs is a source voltage.
As shown in Table 1, in case of the read of data, a voltage of 0V is applied to the source, a voltage of 1V is applied to the drain (bit line connected to cell transistor), a read voltage of 5V is applied to the control gate to determine whether or not a predetermined cell current is flown.
The write of data is carried out for every bit. In the write of data, the voltage of 0V is applied to the source and the voltage of 9V is applied to the control gate. In case that the xe2x80x9c0xe2x80x9d data is written, the voltage of 5V is applied to the drain so that the high energy electron generated by a channel hot electron phenomenon is injected to the floating gate, which causes the threshold voltage Vt to be changed. When the xe2x80x9c1xe2x80x9d data is held, the voltage of 0V is applied to the drain so that the injection of the electron to the floating gate is not occurred, and thus the change in the threshold voltage Vt is not occurred.
The erase of data is carried out collectively to the plurality of cell transistor having the source and the P-well in common. In the erase of data, the voltage of 10V is applied to the source, an erase voltage of xe2x88x927V is applied to the floating gate, and the drain is set to be a floating state. As a result, the electron is flown from the floating gate to the substrate by an F-N tunnel phenomenon, all the target cell transistors for erasing are set to be the xe2x80x9c1xe2x80x9d data.
In order to confirm the write and the erase of data to the cell transistors, write verify and erase verify are carried out.
In the write verify, the read of xe2x80x9c0xe2x80x9d is carried out in a manner that the higher voltage Vpv compared with the voltage in reading is applied to the control gate of the cell transistor. The write and the write verify are carried one after the other, and then the write operation is ended when all the target cell transistors for writing are set to be xe2x80x9c0xe2x80x9d.
In the erase verify, the read of xe2x80x9c1xe2x80x9d is carried out in a manner that the lower voltage Vev compared with the voltage in reading is applied to the control gate of the cell transistor. The erase and the erase verify are carried one after the other, and then the erase operation is ended when a cell current Icell of the target cell transistor for erasing is secured sufficiently (when all the target cell transistors for erasing are set to be xe2x80x9c1xe2x80x9d).
FIG. 12 shows a part of the conventional NOR type flash memory in which a memory core portion has the hierarchical bit line structure.
In FIG. 12, reference numeral 1 is a cell transistor area, 2 is a lower column gate area, 3 is a cell block, 4 is a column reset transistor area, and 5 is an upper column gate area.
That is to say, the memory cell array having cell transistor QC arrayed in a matrix form is divided into the plurality of cell blocks 3 in a longitudinal direction (i.e. column direction) of the upper bit lines MBL0, MBL1, . . . . The upper bit lines MBL0, MBL1, . . . are common for the plurality of cell blocks 3a. 
Operation such as the read and the write is carried out while selecting one of the plurality of cell blocks 3.
In each cell block 3, a plurality of lower bit lines BiBL0, BiBL1, BiBL2, BiBL3, . . . (i=0, 1, . . . ) are provided to extend in the column direction of the memory cell array. Drains of a plurality of cell transistors QC are connected to a corresponding one of the lower bit lines BiBL0, BiBL1, BiBL2, BiBL3, . . . . Also in each cell block 3, a plurality of word lines BiWL0, BiWL1, BiBL2, . . . (i=0, 1, . . . ) are provided to extend in a row direction of the memory cell array. Control gates of a plurality of cell transistors QC are connected to a corresponding one of the word lines BIWL0, BiWL1, BiBL2, . . . . Adjacent two lower bit lines (BiBL0, BiBL1), (BiBL2, BiBL3), . . . of the lower bit lines BiBL0, BiBL1, BiBL2, BiBL3, . . . form one pair. The adjacent two lower bit lines (BiBL0, BiBL1), (BiBL2, BiBL3), . . . are commonly connected to a corresponding one of the upper bit lines MLB0, MLB1, . . . through respective column selection transistors (lower column gates) QLCG. Each of the column selection transistors QLCG is controlled by a signal of a corresponding one of column selection lines BiH0, BiH1, . . . (i=0, 1, . . . ). The lower bit lines BiBL0, BiBL1, BiBL2, BiBL3, . . . comprise metal wirings of a first-stage layer and the upper bit lines MBL0, MBL1, . . . comprise metal wirings of a second-stage layer.
In each cell block 3, a drain of a column reset transistor QCRT is connected to upper bit lines MBL0, MBL1, . . . . In the column reset transistor QCRT, a source of the column reset transistor QCRT is connected to a reset voltage line VRSTi (i=0, 1, . . . ), and a gate of the column reset transistor QCRT is connected to a column reset line COLRSTi (i=0, 1, . . . ).
Each of the upper bit lines MBL0, MBL1, . . . is connected to a data line DL and a sense amplifier 15 through a corresponding one of upper bit line selection transistors (upper column gates) QUCG. Upper column selection lines XiD0, XiD1, . . . (i=0, 1, . . . ) are connected to the gates of the respective upper bit line selection transistors QUCG.
As described later, the column reset transistor QCRT functions to reset charges of bit lines after read operation and also apply a stress voltage to the drain of the cell transistor through bit lines in the drain stress test (bit line test), so that the column reset transistor QCRT is a column-resetting and bit line testing transistor.
FIG. 15 is an example of a circuit diagram of a sense amplifier of the memory shown in FIG. 12;
As shown in FIG. 15, the sense amplifier compares a reference current Iref of a reference cell flowing through the reference data line RDL and a cell current Iload of a memory cell flowing through the cell data line DL and outputs data Dout of the memory cell in accordance with the comparison result.
FIG. 13A shows an example of an operating waveform in case of the read operation in the memory core shown in FIG. 12.
When, for example, the word line B0WL0 is selected and the column line B0H0 is activated (xe2x80x9cHxe2x80x9d level) to select a lower column gate QLCG, a corresponding cell transistor in the cell block 3 of a block number 0 is selected. A voltage dependent on data of the selected cell transistor is appeared on the upper bit line MBL0 through the lower bit line B0BL0. At this time, in case that a column gate selection line X0D0 is the xe2x80x9cHxe2x80x9d level and thus the upper bit line MBL0 is electrically connected to a data line DL, the sense amplifier 15 senses and amplifies a voltage of the data line DL and outputs a cell data in accordance with the comparison result.
When the read operation is ended, the column reset signal line COLRST0 corresponding to the selected cell block 3 of block number 0 is activated (xe2x80x9cHxe2x80x9d level) while the selected lower column gate QLCG is kept activated, so that the charge of the upper bit line MBL0 is discharged through the column resetting transistor QCRT. Since at this time the column reset voltage line VRST0 of the source of the column reset transistor QCRT is set at 0V, an electric potential of the upper bit line MBL0 is reset to 0V.
FIG. 13C is an example of a circuit diagram for generating the bit line reset signal COLRST0. The signal generating circuit comprises an inverter and a NOR circuit. The inverter receives an address transition detection signal ATD and inverts the logic level of the address transition detection signal ATD. The NOR circuit receives the inverted signal output from the inverter and block address inputs BLKADD 0 and BLKADD 1 and generates the bit line reset signal COLRST0.
Transition of internal address signals such as the block address signals BLKADD 0 and BLKADD 1 are completed during the xe2x80x9cHxe2x80x9d level time period.
The bit line reset signal COLRST0 is at the xe2x80x9cHxe2x80x9d level until time T1, as the target cell block, i.e. the cell block to be selected by the block selection signal BLK0 is at the non-selected state. Hence, the bit lines in the target cell block are connected to ground. The target cell block is put into a selected state during the time period from time T1 to time T2, while the bit line reset signal COLRST0 goes to the xe2x80x9cLxe2x80x9d level. Thus, reading of data from the memory cells are carried out. After time T2, the target cell block is again set at a non-selected state and the bit line reset signal COLRST0 goes to the xe2x80x9cHxe2x80x9d level, and thus all of the bit lines in the target cell block are connected to ground.
FIG. 13B shows an example of an operating waveform in case of a drain stress test (bit line test) in the memory core shown in FIG. 12.
In a state that a stress voltage is applied to the drains of the cell transistors while these cell transistors are set at xe2x80x9c0xe2x80x9d data, the threshold voltage after the test of those of the cell transistors which have a defect in the drain side tunnel oxide film portion is lowered. A yield can be increased by performing a redundancy relief for the defective cell transistors.
In the example, in a state that all of the cell transistors in the one or plurality of cell blocks 3 as a target of the test are set at xe2x80x9c0xe2x80x9d data beforehand, the lower column gates QLCG in the selected cell block 3 are turned on and all the upper column gates QUCG are turned off. In this time, the column reset voltage line VRST is set at, for example, a voltage of 5V in writing, the voltage of 5V is applied simultaneously as the stress voltage from the source of the column reset transistor QCRT to the drains of all of the cell transistors in the selected cell block 3 so that a test time is shortened.
Since a gate width of the column reset transistor QCRT is sufficiently small, even though there is a defective leak column in the selected cell block 3, electric potential of other bit lines is not almost affected by the defective leak column.
By the way, a size of transistors has been reduced with developing a micro processing technology. However, scaling of the peripheral transistors such as the column rest transistors QCRT becomes difficult because a thickness of the tunnel oxide films of the cell transistors is not scaled down in order to secure the reliability.
For example, FIG. 14 shows before-scaling and after-scaling arrangements of cell transistors in a cell array area (Cell array) and column reset transistors in a column reset transistor area (Reset transistor).
In the arrangement after scaling, even though the cell transistors in the cell array area are arranged a bit line pitch, the column reset transistors in the column reset transistor area can not be arranged by the bit line pitch. For this reason, a length L of the column reset transistor area is increased, which results in difficulty of higher integration of the semiconductor memory.
In FIG. 14, xe2x80x9cActive areaxe2x80x9d is an active area in the semiconductor substrate (drain, source, and channel regions of a MOSFET). xe2x80x9cGatexe2x80x9d is a gate electrode of the MOSFET. xe2x80x9cConductor wiringxe2x80x9d is a conductor wiring which connects the column selecting cell transistors in the cell array area to the reset transistors in the column reset transistor area.
As described above, there is a disadvantage in the conventional nonvolatile semiconductor memory, that is to say, when scaling of the peripheral transistors such as the column rest transistors become difficult and the column reset transistors can not be arranged by the bit line pitch, then the column reset transistors area becomes large, which results in the difficulty of the higher integration.
According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising a first nonvolatile memory cell and a second nonvolatile memory cell, each of the nonvolatile memory cells holding data; first and second bit lines which are connected correspondingly to the first and second nonvolatile memory cells; first and second column selection transistors connected correspondingly to the first and second bit lines; a first column resetting and bit line testing transistor a drain of which is connected to a first node to which the first and second column selection transistors are commonly connected; a sense amplifier which is selectively connected to the first node and senses and amplifies a cell data appeared on the first node; and a control circuit which controls to turn the first column resetting and bit line testing transistor on to reset an electric potential of the first node, after data of one of the first and second nonvolatile memory cells selected by turning one of the first and second column selection transistors on has been sensed by the sense amplifier in a first time duration, and controls to electrically separate the sense amplifier from the first node while the first and second column selection transistors and the first column resetting and bit line testing transistor are turned on simultaneously in a second time duration.
According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising a first nonvolatile memory cell and a second nonvolatile memory cell a source of each of which is connected to a first common node, each of the first and second nonvolatile memory cells holding data; a third nonvolatile memory cell and a fourth nonvolatile memory cell a source of each of which is connected to a second common node, each of the third and fourth nonvolatile memory cells holding data; first to fourth lower bit lines which are connected correspondingly to the first to fourth nonvolatile memory cells; first to fourth lower column selection transistors one ends of which are connected correspondingly to the first to fourth lower bit lines; a first upper bit line which is connected in common to the other end of each of the first and second lower column selection transistors; a second upper bit line which is connected in common to the other end of each of the third and fourth lower column selection transistors; first and second column resetting and bit line testing transistors, drains of the first and second column resetting and bit line testing transistors being connected corresponding to the first and second upper bit lines; a sense amplifier which is connected selectively to one of the first and second upper bit lines and senses and amplifies a cell data appeared on one of the first and second upper bit lines; and a control circuit which controls to turn one of the first and the second column resetting and bit line testing transistors on to reset an electric potential of one of the first and the second upper bit lines, after data of at least one of the first to fourth nonvolatile memory cells selected by turning at least one of the first to fourth lower column selection transistors on has been sensed by the sense amplifier in an operation time of reading cell data, and controls to electrically separate the sense amplifier from the first and second upper bit lines while the first to fourth lower column selection transistors and the first and second column resetting and bit line testing transistors are turned on simultaneously in a bit line test time.
According to a further of the present invention, there is provided a nonvolatile semiconductor memory comprising a first nonvolatile memory cell and a second nonvolatile memory cell a source of each of which is connected to a first common node, each of the first and second nonvolatile memory cells holding data; a third nonvolatile memory cell and a fourth nonvolatile memory cell a source of each of which is connected to a second common node, each of the third and fourth nonvolatile memory cells holding data; first to fourth lower bit lines which are connected correspondingly to the first to fourth nonvolatile memory cells; first to fourth lower column selection transistors one ends of which are connected correspondingly to the first to fourth lower bit lines; a first upper bit line which is connected to the other ends of the first to fourth lower column selection transistors; first column resetting and bit line testing transistor, a drain of the first column resetting and bit line testing transistor being connected to the first upper bit line; a sense amplifier which is connected selectively to one of the first upper bit line and senses and amplifies a cell data appeared on the first upper bit line; and a control circuit which controls to turn one of the first column resetting and bit line testing transistor on to reset an electric potential of the first upper bit line, after data of at least one of the first to fourth nonvolatile memory cells selected by turning at least one of the first to fourth lower column selection transistors on has been sensed by the sense amplifier in an operation time of reading data, and controls to electrically separate the sense amplifier from the first upper bit line while the first to fourth lower column selection transistors and the first column resetting and bit line testing transistor are turned on simultaneously in a bit line test time.
According to a further of the present invention, there is provided a nonvolatile semiconductor memory comprising a memory cell array including a plurality of nonvolatile memory cells arranged in a matrix form, each of the nonvolatile memory cells having a laminated gate in which a floating gate and a control gate are laminated, memory cell array being divided into a plurality of cell blocks in a column direction; first and second lower bit lines which are provided in each of the cell blocks, the first and second lower bit lines being connected correspondingly to first and second nonvolatile memory cells holding data; first and second column selection transistors which are provided in each of the cell blocks, the first and second column selection transistors being connected correspondingly to the first and second lower bit lines; an upper bit line which is provided commonly for the plurality of cell blocks in a column direction, the first and second column selection transistors in the cell blocks being commonly connected to the upper bit line; a column resetting and bit line testing transistor, a drain node of the column resetting and bit line testing transistor being connected to the upper bit line; a sense amplifier which is selectively connected to the upper bit line to sense and amplify data appeared on the upper bit line; and a control circuit which controls to turn on the column resetting and bit line testing transistor connected to one of the upper bit lines to reset an electric potential of the upper bit line, after data of one of the first and second nonvolatile memory cells selected by turning on one of the first and second lower column selection transistors in a selected cell block of the plurality of cell blocks are sensed by the sense amplifier through the one upper bit line which corresponds to the selected cell block in an operation time of reading data, and controls to electrically separate the sense amplifier from the one upper bit line while the first and second lower column selection transistors in the selected cell block of the plurality of cell blocks and the column resetting and bit line testing transistor connected to the upper bit line corresponding to the selected cell block are turned on simultaneously in a bit line test.
According to a further of the present invention, there is provided a nonvolatile semiconductor memory comprising a memory cell array including a plurality of nonvolatile memory cells arranged in a matrix form, each of the nonvolatile memory cells having a laminated gate in which a floating gate and a control gate are laminated, memory cell array being divided into a plurality of cell blocks in a row direction and a column direction; first and second lower bit lines which are provided in each of the cell blocks, the first and second lower bit lines being connected correspondingly to first and second nonvolatile memory cells holding data; first and second column selection transistors which are provided in each of the cell blocks, the first and second column selection transistors being connected correspondingly to the first and second lower bit lines; a plurality of upper bit lines which are provided commonly for the plurality of cell blocks and correspondingly provided for columns, the first and second column selection transistors in those of the cell blocks which are in the same column being commonly connected to a corresponding one of the plurality of upper bit lines; a plurality of column resetting and bit line testing transistors, a drain node of each of the column resetting and bit line testing transistors being connected to a corresponding one of the plurality of upper bit lines; a sense amplifier which is selectively connected to the plurality of upper bit lines to sense and amplify data appeared on the upper bit lines; and a control circuit which controls to turn on the column resetting and bit line testing transistor connected to one of the upper bit lines to reset an electric potential of the upper bit line, after data of one of the first and second nonvolatile memory cells selected by turning on one of the first and second lower column selection transistors in a selected cell block of the plurality of cell blocks are sensed by the sense amplifier through the one upper bit line which corresponds to the selected cell block in an operation time of reading a cell data, and controls to electrically separate the sense amplifier from the one upper bit line while the first and second lower column selection transistors in the selected cell block of the plurality of cell blocks and the column resetting and bit line testing transistor connected to the upper bit line corresponding to the selected cell block are turned on simultaneously in a bit line test.